Since the inception of the semiconductor industry, photolithography has been used for forming the components of integrated circuits. Generally, light beams pass through a mask, which has been patterned with a magnified image of the relevant integrated circuits. The light beams are then focused by a projection lens onto a wafer, resulting in an image of the integrated circuits in the photoresist layer of the wafer.
Among other factors, mask defects constitute a source of yield reduction. Specifically, the deviation of the mask image will result in the imperfection of the image on the wafer.
Even though the defects of the mask image are detected during mask verification and validation, traditional approaches for wafer fabrication fail to take advantage of such information. As shown in FIG. 1, after a customer 2 completes the design of the integrated circuits, the design data may be stored in a tape and forwarded to a mask formation unit 4 for purposes of generating a corresponding mask. Then, the completed mask may be dispatched to a wafer fabrication unit 6 to be used for semiconductor integrated circuit fabrication. Because mask formation is often imperfect and causes deviation in mask dimensions, wen the wafer fabrication facility performs mask verification and validation, a trial-and-error process is often used, which results in wasted time, funds and energy. The resultant product cycle time for product verification and validation and time-to-market is prolonged. This problem is only aggravated by the shrinking device dimensions.